Xilinx FPGA逻辑资源等效门

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Equivalent ASIC gate count    是等效成的ASIC中门电路的数量，那么对于一个给定的FPGA，如何计算它的等效门数量呢？

首先看一张kintex-7系列FPGA的资源表：

表格解读：对于XC7k70T这个器件，它大概有70k个logic cell，而根据Xilinx官方文档中的解释，每一个7系列FPGA Slice包含4个LUT和8个寄存器。

下面这段文字主要阐述logic cell和LUT之间的关系，总结一下就是，一个4输入LUT等效成1.25个logic cell，而一个6输入LUT等效成1.6个logic cell，因此XC7K70T 这个器件有10250个slice，那个6输入LUT就是x4：41000，寄存器数量是x8:82000，logic cell数量是LUT x 1.6 = 41000 x 1.6 = 65600.

A "logic cell" is a marketing thing. It is an attempt to create a "unified" metric that can be used across different device families (and even different vendors) to compare sizes of devices even when the underlying architecture is different.

The "logic cell" is supposed to represent a 4-input LUT with no other functionality. In older Xilinx technologies (with 4-input LUTs) they used to use 1.25 as the multiplier to get from LUTs to Logic Cells, since the Xilinx slice also had the carry chain and wide MUX, which made it possible to do more than a simple 4-input LUT would be able to do.

In later technologies, which use the 6-input LUT, they use the multiplier 1.6.

Also remember there are two flip-flops per LUT...

So, the device has 2,443,200 flip-flops, which means 1,221,600 6-input LUTs. Multiply this by 1.6 and you get 1,945,560, which is the published "Logic Cells" number.

那么logic cell与slice、LUT之间的关系明确之后，如何根据logic cell计算等效门电路数量呢？

在Xilinx官方文档中有这么一句话：Equivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.

就是说，通常情况下一个logic cell大概等效成15个 ASIC  gate

，因此把logic cell 乘以这个系数15就可以得到这个器件的等效门电路数量。

参考资料：

https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/logic-cell-vs-CLB/td-p/743699

ds180_7Series_Overview.pdf

7-series-product-selection-guide.pdf

xa-zynq-7000-product-table.pdf

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